Field of the Invention
The present invention relates to digital sequential logic circuits, and in particular to a method for automatically eliminating hold time violations in a system for implementing logic circuitry from a user net list or prototype configuration.
As electronic components and electronic systems grow more complex, the design of these components and systems has become a more time-consuming and demanding task. Recently, emulation of electronic components and systems has emerged as an important tool for designers. Simulation systems now include apparatus which aids in the development of integrated circuits and systems design by quickly and automatically generating a hardware prototype of an integrated circuit or system to be designed from a user's schematics or net list. Such an apparatus is described in U.S. patent application Ser. No. 279,477. In such systems, a prototype circuit is electrically reconfigurable and may be modified to represent an indefinite number of designs with no manual wiring changes or device replacement. The prototype circuit runs at real time or very closely approximates real time speed and may be incorporated into a larger system. Also, VLSI chips or ASIC devices may be plugged into a prototype circuit and run as part of the emulated design.
When designing such circuitry, it is important to implement the necessary logic functions and to connect them together into a complete and functioning design. Synchronization requires that data arrive at a logic device such as a flip-flop at an appropriate time relative to a clock pulse. There is a specified "setup time" and "hold time" for any clocked device. Setup time requires that input data must be present at the data input lead of a flip-flop device and in stable form for a predetermined amount of time before the clock transition. Hold time requires that the data be stable from the time of the clock transition on arrival at the control lead of a flip-flop up to a certain time interval after the arrival of the clock for proper operation. For example, the so called 7474 TTL positive edge triggered D type flip-flop has a setup time of 20 nanoseconds and a hold time of 5 nanoseconds. When implementing a circuit from user net list data containing thousands of flip-flop devices, any violation of the stringent hold time or setup time parameters would prevent proper operation of the implemented circuit. A key process in implementing a logic circuit from a user's net list is to synchronize the setup and hold time of data with the arrival of a corresponding clock. Data must be present and stable at the D input of a flip-flop for a specific space of time with respect to the arrival of the corresponding clock at the clock input to ensure the proper operation of the implemented logic circuit.
It will be appreciated that setup time violations may be remedied simply by slowing down the speed at which the design is clocked. Hold time violations, however, persist regardless of clock speed and depend only on the clock skew in various parts of the design.
Therefore, in implementing a circuit from user net list data, the proper timing of clock signals may be hindered due to excessive delay in the clock lines by reason of clock skew. This may cause data in a first logic device such as a flip-flop or shift register to shift earlier than data on a second register. The hold time requirement of the second register is violated and data bits may then be lost unless the shift registers are properly synchronized.
It is to be expected that in an implementation of a high-speed logic system from a user net list, thousands of logic devices such as flip-flops must be duplicated and synchronized with extreme precision. A problem that may arise in such an implementation is that skew on the clock lines may develop so that a flip-flop may actually receive data caused by a clock before it receives the clock signal itself. In that case, the flip-flop would not be able to clock in the intended data, as that data would have been overwritten by newer data.
It is apparent therefore that what is needed is a method for eliminating hold time violations even in the presence of massive clock skew in order to facilitate the implementation of a high-speed logic circuit from a user net list. Such a method for eliminating hold time violations would advantageously be implemented in an automatic manner. This would eliminate the need to manually synchronize the proper arrival of clocks and setup and hold time of data by trial and error techniques.
One prior art method for synchronizing a clock distribution system is described in the article, "CURRENT TECHNOLOGY AND DESIGN METHODOLOGY FOR SYSTEM DESIGNERS, J. Zasio, WESCON Conference Record, Nov. 14-15, 1989." This method suggests the use of level triggered latches and a two phase non-overlapping clock. As long as the two clock phases do not overlap, there will be no hold time violations. However, this prior art method has the disadvantage of doubling the number of clocks for the combinatorial logic to be emulated. Thus, it is apparent that what is needed is an automatic method for eliminating hold time violations which does not unduly increase the complexity of the prototype circuit.